Competitive Advantages
- Scalable
- Mitigate llimit cycle oscillations
- Lower area overhead
- Reduces aging induced degradations
Summary
USF inventors have developed a reduced clock pulse width digital low-dropout regulator. Instead of using a conventional square wave as clock signal, a clock signal with reduced pulse width is utilized. With this design, the number of regulators utilized in the system and the size of each local regulator are scalable to satisfy the needs of different applications. It is demonstrated through simulation of an IBM POWER8 like processor that the proposed aging-aware design can achieve up to, respectively, 43.2% and 3X transient and steady state performance improvement. Additionally, more than 10% area overhead saving can be achieved over a five-year period.
Schematic of The Aging-Aware DLDO
Desired Partnerships
- License
- Sponsored Research
- Co-Development